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d a t a sh eet preliminary speci?cation file under integrated circuits, ic02 1996 aug 13 integrated circuits SAB9076H picture-in-picture (pip) controller
1996 aug 13 2 philips semiconductors preliminary speci?cation picture-in-picture (pip) controller SAB9076H features display twin pip in interlaced mode at 8-bit resolution sub-title mode features built in large display fine positioning area, both channels independent only 2 mbit required as external vdram (2 1 mbit or 1 2 mbit) four 8-bit analogue digital converters (adcs; > 7-bit performance) with clamp circuit most pip modes handle interlaced pictures without joint line error two plls which generate the line-locked clocks for the acquisition channels display pll to generate line-locked clock for the display three 8-bit digital analogue converters (dacs) 4:1:1 data format data reduction factors 1 to 1, 1 to 2, 1 to 3 and 1 to 4, horizontal and vertical independent. i 2 c-bus programmable single and double pip modes can be set full field still mode available several aspect ratios can be handled reduction factors can be set freely selection of vertical filtering type freeze of live pictures fine tuned display position, h (8-bit), v (8-bit), both channels independent fine tuned acquisition area, h (4-bit), v (8-bit), both channels independent eight main borders, sub-borders and background colours selectable border and background brightness adjustable, 30%, 50%, 70% and 100% ire several type of decoder input signals can be set. general description the SAB9076H is a picture-in-picture controller for ntsc tv-sets. the circuit contains adcs, reduction circuitry, memory control, display control and dacs. the device inserts one or two live video signals with original or reduced sizes into a live video signal. all video signals are expected to be analog baseband signals. the conversion into the digital environment and back to the analog environment is carried out on chip. internal clocks are generated by two acquisition plls and a display pll. due to the two pip channels and a large external memory a wide range of pip modes are offered. the emphasis is put on single-pip, double-pip, split-screen mode and a many multi-pip modes.
1996 aug 13 3 philips semiconductors preliminary speci?cation picture-in-picture (pip) controller SAB9076H quick reference data note 1. the internal system frequency is 1728 times the h sync input frequency for both the acquisition and display plls. ordering information note 1. when using ir reflow soldering it is recommended that the drypack instructions in the quality reference handbook (order number 9398 510 63011) are followed. symbol parameter conditions min. typ. max. unit v dd supply voltage 4.5 5.0 5.5 v i dd supply current - 200 - ma f sys system frequency note 1 - 27 - mhz f loop pll loop bandwidth frequency 4 -- khz t jitter pll short term stability time jitter during 1 line (64 m s) -- 4ns v pll damping factor - 0.7 -- type number package name description version SAB9076H qfp100 (1) plastic quad ?at package; 100 leads (lead length 1.95 mm); body 14 20 2.8 mm sot317-2
1996 aug 13 4 philips semiconductors preliminary speci?cation picture-in-picture (pip) controller SAB9076H block diagram h andbook, full pagewidth mgc962 sy su sv sav bias mav ddd mav ssd mav dda mav ssa sav reft sav refb 71 3 4 12 11 dav ddd dav ssd dav dda dav ssa taclk tc tdclk tm2 tm1 tm0 a0 scl sda por mcv ddd mcv ssd dcv ssd dcv ddd dv ddd dv ssd v ssd v ddd scv ssd scv ddd spv dda spv ssa dpv ssa dpv dda mpv dda mpv ssa 91 92 84 83 100 63 18 19 22 21 20 15 16 59 60 61 62 82 81 41 42 43 44 45 46 65 66 97 98 99 sav ddd sav ssd sav dda sav ssa 78 77 69 70 sv ddd sv ssd mv ddd mv ssd 68 67 13 14 cas ras 49 48 dao0 to dao7 47 31 40 32, 34, 36, 38, 39, 37, 35, 33 dai0 to dai7 23, 25, 27, 29, 30, 28, 26, 24 ad0 to ad8 51, 53, 55, 57, 58, 56, 54, 52, 50 75 73 76 74 72 dy du dv dav bias dav reft dav refb 86 90 88 85 87 89 dfb 93 dt we sc dac and buffer clamp and adc my mu mv mav bias mav reft mav refb 10 6 8 5 7 9 clamp and adc sph sync sv sync spv bias 79 64 80 pll and clock generator horizontal and vertical filter horizontal and vertical filter mph sync mv sync mpv bias 2 17 1 pll and clock generator dph sync dv sync dpv bias 96 94 95 pll and clock generator line memory vdram control and (re-) formatting display control line memory i 2 c-bus control line memory SAB9076H fig.1 block diagram.
1996 aug 13 5 philips semiconductors preliminary speci?cation picture-in-picture (pip) controller SAB9076H pinning symbol pin i/o type description mpv bias 1 i/o e027 analog bias reference for main channel mph sync 2 i hpp01 horizontal synchronization input for main channel mav ssd 3 i/o e009 digital ground for main channel adcs and plls mav ddd 4 i/o e030 digital positive power supply for main channel adcs and plls mav bias 5 i e027 analog bias reference input for main channel adcs mu 6 i e027 analog u input for main channel mav reft 7 i e027 analog top reference voltage input for main channel adcs mv 8 i e027 analog v input for main channel mav refb 9 i e027 analog bottom reference voltage input for main channel adcs my 10 i e027 analog y input for main channel mav dda 11 i/o e030 analog positive power supply for main channel adcs mav ssa 12 i/o e009 analog ground for main channel adcs mv ssd 13 i/o e009 digital ground for main-channel core mv ddd 14 i/o e030 digital positive power supply for main-channel core mcv ddd 15 i/o e030 digital positive power supply for main-clock buffer mcv ssd 16 i/o e009 digital ground for main-clock buffer mv sync 17 i hpp01 vertical synchronization input for main channel tdclk 18 i hpp01 test clock input for display tc 19 i hpp01 test control input tm0 20 i hpp01 test mode 0 input tm1 21 i hpp01 test mode 1 input n.c. 22 -- not connected dai0 23 i hpp01 data bus input from memory; bit 0 dai7 24 i hpp01 data bus input from memory; bit 7 dai1 25 i hpp01 data bus input from memory; bit 1 dai6 26 i hpp01 data bus input from memory; bit 6 dai2 27 i hpp01 data bus input from memory; bit 2 dai5 28 i hpp01 data bus input from memory; bit 5 dai3 29 i hpp01 data bus input from memory; bit 3 dai4 30 i hpp01 data bus input from memory; bit 4 dt 31 o opf20 memory data transfer output; active low dao0 32 o opf20 data bus output to memory; bit 0 dao7 33 o opf20 data bus output to memory; bit 7 dao1 34 o opf20 data bus output to memory; bit 1 dao6 35 o opf20 data bus output to memory; bit 6 dao2 36 o opf20 data bus output to memory; bit 2 dao5 37 o opf20 data bus output to memory; bit 5 dao3 38 o opf20 data bus output to memory; bit 3 dao4 39 o opf20 data bus output to memory; bit 4 sc 40 o opf20 memory shift clock output
1996 aug 13 6 philips semiconductors preliminary speci?cation picture-in-picture (pip) controller SAB9076H dcv ssd 41 i/o e009 digital ground for display-clock buffer dcv ddd 42 i/o e030 digital positive power supply for display-clock buffer dv ddd 43 i/o e030 digital positive power supply for display core dv ssd 44 i/o e009 digital ground for display core v ssd 45 i/o e009 digital ground for peripherals v ddd 46 i/o e030 digital positive power supply for peripherals we 47 o opf20 memory write enable output; active low cas 48 o opf20 memory column address strobe output; active low ras 49 o opf20 memory row address strobe output; active low ad8 50 o opf20 memory address bus output; bit 8 ad0 51 o opf20 memory address bus output; bit 0 ad7 52 o opf20 memory address bus output; bit 7 ad1 53 o opf20 memory address bus output; bit 1 ad6 54 o opf20 memory address bus output; bit 6 ad2 55 o opf20 memory address bus output; bit 2 ad5 56 o opf20 memory address bus output; bit 5 ad3 57 o opf20 memory address bus output; bit 3 ad4 58 o opf20 memory address bus output; bit 4 a0 59 i hpf01 i 2 c-bus address 0 selection input scl 60 i hpf01 shift clock input for i 2 c-bus sda 61 i/o ioi41 shift i 2 c-bus input data; acknowledge i 2 c-bus output data por 62 i hup07 power-on reset input taclk 63 i hpp01 test clock input for acquisition sv sync 64 i hpp01 vertical synchronization input for sub-channel scv ssd 65 i/o e009 digital ground for sub-clock buffer scv ddd 66 i/o e030 digital positive power supply for sub-clock buffer sv ddd 67 i/o e030 digital positive power supply for sub-channel core sv ssd 68 i/o e009 digital ground for sub-channel core sav ssa 69 i/o e009 analog ground for sub-channel adcs sav dda 70 i/o e030 analog positive power supply for sub-channel adcs sy 71 i e027 analog y input for sub-channel sav refb 72 i e027 analog bottom reference input voltage for sub-channel adcs sv 73 i e027 analog v input for sub-channel sav reft 74 i e027 analog top reference input voltage for sub-channel adcs su 75 i e027 analog u input for sub-channel sav bias 76 i/o e027 analog bias reference input/output for sub-channel adcs sav ddd 77 i/o e030 digital positive power supply for sub-channel adcs and plls sav ssd 78 i/o e009 digital ground for sub-channel adcs and plls sph sync 79 i hpp01 horizontal synchronization input for sub-channel spv bias 80 i/o e027 analog bias reference input/output for sub-channel spv ssa 81 i/o e009 analog ground for sub-channel pll symbol pin i/o type description
1996 aug 13 7 philips semiconductors preliminary speci?cation picture-in-picture (pip) controller SAB9076H table 1 pin type explanation spv dda 82 i/o e030 analog positive power supply for sub-channel pll dav dda 83 i/o e030 analog positive power supply for dacs dav ssa 84 i/o e009 analog ground for dacs dav bias 85 i e027 analog bias voltage reference input for dacs dy 86 o e027 analog y output of dac dav reft 87 i e027 analog top reference input voltage for dacs dv 88 o e027 analog v output of dac dav refb 89 i e027 analog bottom reference input voltage for dacs du 90 o e027 analog u output of dac dav ssd 91 i/o e009 digital ground for dacs dav ddd 92 i/o e030 digital positive power supply for dacs dfb 93 o opf20 fast blanking control output signal dv sync 94 i hpp01 vertical synchronization input for display channel dph sync 95 i hpp01 horizontal synchronization input for display pll dpv bias 96 i/o e027 analog bias voltage reference input/output for display pll dpv ssa 97 i/o e009 analog ground for display pll dpv dda 98 i/o e030 analog positive power supply for display pll mpv dda 99 i/o e030 analog positive power supply for main channel pll mpv ssa 100 i/o e009 analog ground for main channel pll pin type description e030 v dd pin; diode to v ss e009 v ss pin; diode to v dd e027 analog input pin; diode to v dd and v ss hpf01 digital input pin; cmos levels, diode to v ss hpp01 digital input pin; cmos levels, diode to v dd and v ss hup07 digital input pin; cmos levels with hysteresis, pull-up resistor to v dd , diode to v dd and v ss ioi41 i 2 c-bus pull-down output stage; cmos input levels, diode to v ss opf20 digital output pin; cmos levels symbol pin i/o type description
1996 aug 13 8 philips semiconductors preliminary speci?cation picture-in-picture (pip) controller SAB9076H handbook, full pagewidth 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 mgc963 SAB9076H mpv bias mph sync mav ssd mav ddd mav bias mu mav reft mv mav refb my mav dda mav ssa mv ssd mv ddd mcv ddd mcv ssd mv sync tdclk tc tm0 tm1 n.c. dai0 dai7 dai1 dai6 dai2 dai5 dai3 dai4 dt dao0 dao7 dao1 dao6 dao2 dao5 dao3 dao4 sc dcv ssd dcv ddd dv ddd dv ssd v ssd v ddd we cas ras ad8 spv bias sph sync sav ssd sav ddd sav bias su sav reft sv sav refb sy sav dda sav ssa sv ssd sv ddd scv ddd scv ssd sv sync taclk por sda scl a0 ad4 ad3 ad5 ad2 ad6 ad1 ad7 ad0 mpv ssa mpv dda dpv dda dpv ssa dpv bias dph sync dv sync dfb dav ddd dav ssd du dav refb dv dav reft dy dav bias dav ssa dav dda spv dda spv ssa fig.2 pin configuration.
1996 aug 13 9 philips semiconductors preliminary speci?cation picture-in-picture (pip) controller SAB9076H functional description pixel rate the internal chrominance format used is 4 : 1 : 1. it is expected that the bandwidth of the input signals is limited to 4.5 mhz for the y input and 1.125 mhz for the u/v input. the y input is sampled with a 1728 hs ( ? 27.0 mhz) clock and is filtered and down sampled to the internal 864 hs ( ? 13.5 mhz) pixel rate. the u and v inputs are multiplexed and sampled with a 432 hs clock and down sampled to the internal 216 hs ( ? 3.375 mhz) pixel rate. acquisition area synchronisation is achieved via the acquisition h sync and v sync pins. with the acquisition fine positioning added to a system constant the starting point of the acquisition can be controlled. the acquisition area is 672 pixels/line and 228 lines/field for ntsc. both main and sub-channels are equivalent in handling the data. display mode the internal display pixel rate is 864 dph sync which is 13.5 mhz. this pixel rate is up sampled by interpolation to 1728 dph sync before the dac stage. display area the display background is an area of 696 pixels and 238 lines. this can be put on/off by the bgon bit independent of the pipon bit. this area can be moved by the display background fine positioning (bghfp and bgvfp registers). its colour is determined by the bgcol and bgbrt registers. within this area pips are defined dependent on the pip mode. the pip sizes are determined by the display reduction factors as is shown in table 2. the display fine positioning determines the location of the pips with respect to the background. sub-channel and main channel both have their independent pip size and location control, which is shown in fig.3. table 2 pip sizes reduction h/1 h/2 h/3 h/4 v/1 v/2 v/3 v/4 pixels 672 336 224 168 ---- lines ---- 228 114 76 57
1996 aug 13 10 philips semiconductors preliminary speci?cation picture-in-picture (pip) controller SAB9076H fig.3 display fine positioning. handbook, full pagewidth mgc964 bghfp bgvfp main channel sub channel sahfp mavfp 238 lines mahfp savfp 696 pixels pip modes the two independent acquisition channels can be controlled independently on the display side. a wide variety of modes is possible but a subset of 7 modes is fixed and can be set easily by the i 2 c-bus. an overview of the preconditioned modes is given in table 3. for all pip modes the main and sub-display fine positioning must be set to obtain a display configuration. d ata transfer the internal data path has an 8-bit resolution and 4 :1:1 data format. the communication to the external vdram takes place at 864 h sync (both display and acquisition). approximately 800 8-bit words can be fetched from the external vdram in one display line which is not enough to display one complete display line with true 8-bit resolution. two methods of reducing data are available. one is simply skipping the 8-bit to 6-bit (skip6, i 2 c-bus bit) and the other is a small form of data reduction to come from 8-bit to 6-bit (smart6, i 2 c-bus bit). if both bits are set to logic 0 the device is in true 8-bit resolution mode. for the twin pip mode the main channel is not placed in the vdram but in an internal buffer, so still 8-bit resolution is achieved.
1996 aug 13 11 philips semiconductors preliminary speci?cation picture-in-picture (pip) controller SAB9076H table 3 pip modes pip combinations figures 4, 5 and 6 provide an overview of possible combinations as they can be shown on the screen. an example of fine positioning is given in the right four columns of table 3. more pip modes can be obtained by varying the horizontal and vertical reduction factors to meet correct aspect ratios when using 16 : 9 screens. pip modes sub-channel main channel sub-channel main channel name figure mode redh redv redh redv hfp vfp hfp vfp sp sp small 0000 1 4 1 4 ------ sp sp medium 0000 1 3 1 3 ------ sp sp large 0000 1 2 1 2 ------ sp sp small 0000 -- 1 4 1 4 --- - sp sp medium 0000 -- 1 3 1 3 --- - sp sp large 0000 -- 1 2 1 2 --- - dp dp 0000 1 2 1 2 1 2 1 2 03h 46h 57h 46h dp twin pip 1001 1 2 1 1 1 2 1 1 03h 05h 57h 05h mp3l pop-left 0010 1 4 1 4 -- 08h 46h -- mr3r pop-right 0010 -- 1 4 1 4 -- 72h 10h mr3d pop-double 0010 1 4 1 4 1 4 1 4 08h 10h 72h 10h mp7 pop-double 0011 1 4 1 4 -- 03h 05h -- mp8 mp7 0011 1 4 1 4 1 2 1 2 03h 05h 44h 20h mp4 quatro 0001 1 2 1 2 1 2 1 2 03h 05h 03h 77h mp9 mp9 0100 1 3 1 3 1 3 1 3 03h 05h 51h 3bh mp16 mp16 0101 1 4 1 4 -- 03h 05h 03h 05h mp16 mp16 mix 0110 1 4 1 4 1 4 1 4 03h 05h 03h 77h ffs full ?eld still 0000 1 1 1 1 -- 03h 05h -- ffl full ?eld live 1000 -- 1 1 1 1 -- 03h 05h man manual 0111 x x x x x x x x
1996 aug 13 12 philips semiconductors preliminary speci?cation picture-in-picture (pip) controller SAB9076H fig.4 pip modes. handbook, halfpage mgd588 pop-left handbook, halfpage mgd598 twin-pip handbook, halfpage mgd594 sp-small handbook, halfpage mgd595 sp-medium handbook, halfpage mgd596 sp-large handbook, halfpage mgd597 dp
1996 aug 13 13 philips semiconductors preliminary speci?cation picture-in-picture (pip) controller SAB9076H fig.5 pip modes (continued). handbook, halfpage mgd589 pop-right handbook, halfpage mgd590 pop-double handbook, halfpage mgd591 mp7 handbook, halfpage mgd592 mp8 handbook, halfpage mgd593 mp13 handbook, halfpage mgd584 quatro
1996 aug 13 14 philips semiconductors preliminary speci?cation picture-in-picture (pip) controller SAB9076H fig.6 pip modes (continued). handbook, halfpage mgd585 mp9 handbook, halfpage mgd586 mp16 handbook, halfpage mgd587 full field still full field live
1996 aug 13 15 philips semiconductors preliminary speci?cation picture-in-picture (pip) controller SAB9076H i 2 c-bus description the i 2 c-bus provides bi-directional 2-line communication between different ics. the sda line is the serial data line and scl serves as serial clock line. both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. data transfer may be initiated only when the bus is not busy. the SAB9076H has the i 2 c-bus addresses 2c and 2e, switchable by the pin a0. valid sub-addresses (sa) are 00h to 18h (table 4) and 20h to 32h (table 6). i 2 c-bus control is in accordance with the i 2 c-bus protocol. first a start sequence must be put on the i 2 c-bus, then the i 2 c-bus address of the circuit must be send, followed by a subaddress. after this sequence the data of the subaddresses must be sent. an auto-increment function gives the option to send data of the incremented subaddresses until a stop sequence is send. table 4 gives an overview of the i 2 c-bus addresses. table 4 overview of i 2 c-bus sub-addresses note 1. the data bits which are not used should be set to zero. sa data byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00h mpipon spipon mfreeze sfreeze pipmode3 pipmode2 pipmode1 pipmode0 01h note 1 note 1 m1fld s1fld note 1 dnonint mnonint snonint 02h dfilt filloff smart6 skip6 yth3 yth2 yth1 yth0 03h bghfp3 bghfp2 bghfp1 bghfp0 bgvfp3 bgvfp2 bgvfp1 bgvfp0 04h sdhfp7 sdhfp6 sdhfp5 sdhfp4 sdhfp3 sdhfp2 sdhfp1 sdhfp0 05h sdvfp7 sdvfp6 sdvfp5 sdvfp4 sdvfp3 sdvfp2 sdvfp1 sdvfp0 06h mdhfp7 mdhfp6 mdhfp5 mdhfp4 mdhfp3 mdhfp2 mdhfp1 mdhfp0 07h mdvfp7 mdvfp6 mdvfp5 mdvfp4 mdvfp3 mdvfp2 mdvfp1 mdvfp0 08h mdredh1 mdredh0 mdredv1 mdredv0 sdredh1 sdredh0 sdredv1 sdredv0 09h maredh1 maredh0 maredv1 maredv0 saredh1 saredh0 saredv1 saredv0 0ah mahfp3 mahfp2 mahfp1 mahfp0 sahfp3 sahfp2 sahfp1 sahfp0 0bh savfp7 savfp6 savfp5 savfp4 savfp3 savfp2 savfp1 savfp0 0ch mavfp7 mavfp6 mavfp5 mavfp4 mavfp3 mavfp2 mavfp1 mavfp0 0dh mlsel3 mlsel2 mlsel1 mlsel0 slsel3 slsel2 slsel1 slsel0 0eh mbsel3 mbsel2 mbsel1 mbsel0 sbsel3 sbsel2 sbsel1 sbsel0 0fh bhsize3 bhsize2 bhsize1 bhsize0 bvsize3 bvsize2 bvsize1 bvsize0 10h note 1 sbon sbbrt1 sbbrt0 note 1 sbcol2 sbcol1 sbcol0 11h note 1 sbson sbsbrt1 sbsbrt0 note 1 sbscol2 sbscol1 sbscol0 12h note 1 mbon mbbrt1 mbbrt0 note 1 mbcol2 mbcol1 mbcol0 13h note 1 mbson mbsbrt1 mbsbrt0 note 1 mbscol2 mbscol1 mbscol0 14h note 1 bgon bgbrt1 bgbrt0 note 1 sbgcol2 sbgcol1 sbgcol0 15h note 1 note 1 note 1 svfilt suvpol svspol shsync sfpol 16h note 1 note 1 note 1 mvfilt muvpol mvspol mhsync mfpol 17h note 1 fbdel2 fbdel1 fbdel0 duvpol dvspol dhsync dfpol 18h pedestv3 pedestv2 pedestv1 pedestv0 pedestu3 pedestu2 pedestu1 pedestu0
1996 aug 13 16 philips semiconductors preliminary speci?cation picture-in-picture (pip) controller SAB9076H sa 00h pip register the mpipon and spipon bits switch respectively the main and sub pips of the SAB9076H on or off. the mfreeze and sfreeze bits make the current live pictures for the channels main and sub frozen. the writing to the vdram is stopped. the pipmode3 to pipmode0 bits set the pip mode in accordance with table 3. sa 01h display register the m1fld and s1fld (1) bits control the use of the reserved second field in the vdram. if this bit is set to logic 0 then address spaces are reserved for both fields in the vdram. this avoids joint line errors. whether these address spaces are used is dependent on the interlacing of the input signals and the three nonint bits. if a 1fld bit is set to logic 1 then only 1 address space is used in the vdram for both fields. in some pip modes the use of a second field is not possible since there is not enough space in the vdram, in these modes the 1fld bit must be set to logic 1. dnonint controls the interlace mode of the display part. if set to logic 1 then data is only read from one field in the vdram. if set to logic 0 then both fields (if available) are used for display. the mnonint and snonint bits control the interlace mode of the acquisition blocks. if set to logic 1 then data is only written to one field in the vdram (two fields remain allocated). if set to logic 0 then both fields (if available) are used for acquisition. sa 02h display register the dfilt bit controls an interpolating filter that changes the internal 864 pixels data rate to the output data rate of 2 864 pixels. if dfilt is set to logic 1 then the filter is on. the filloff bit controls filling of pips when the pip mode is switched. if filloff is set to logic 0 then all pips are filled with a 30% gray until their channel has been updated. if filloff is set to logic 1 then the vdram content is always visible. this is useful when a new, similar to the previous one, pip mode is set. the previous data can then be displayed. the smart6 and skip6 bits control the data transfer mode to the external vdram. for modes which display a complete line (672 pixels) a type of data reduction has to be carried out. two transfer modes are available. one is simply skipping the 8-bit data path to 6-bit (skip6). the other is carry out an intelligent data reduction which retains an 8-bit resolution (smart6). (1) the 1 fld bits only operate when the nonint bits of the corresponding channel is set. the yth3 to yth0 bits control the video output. if the current y-value is less then yth 16 then the fast blank is switched off, the original live background will be visible. this feature can be used to pick up sub-titles and display them as on-screen display (osd) anywhere on the screen. sa 03h display background fine positioning register the bghfp3 to bghfp0 bits control the horizontal display positioning of the background. the resolution is 16 steps of 4 pixels. the bgvfp3 to bgvfp0 bits control the vertical display positioning of the background. the resolution is 16 steps of 2 lines/field. the background fine positioning moves the complete display. it is a general offset of all the pip pictures and background. it is intended only to adjust once the centring of all pip modes (see fig.3). sa 04h and sa 05h display sub - channel fine positioning registers these registers control the horizontal and vertical fine positioning of the display sub-channel with respect to the display background. this is the actual fine positioning (see fig.3). the horizontal resolution is 256 steps of 4 pixels and the vertical resolution is 256 steps of 1 line/field. sa 06h and sa 07h display main - channel fine positioning registers these registers control the horizontal and vertical fine positioning off the display main-channel with respect to the display background. this is the actual fine positioning (see fig.3). the horizontal resolution is 256 steps of 4 pixels and the vertical resolution is 256 steps of 1 line/field. sa 08h display reduction factors register this register sets the display reduction factors, independent of the acquisition reduction factors. it sets the pip size to a certain default value in such a way that the border drawn around the pip is just fitting. sa 09h acquisition reduction factors register this register sets the acquisition reduction factors, independent of the display reduction factors. if the hred is 1 : 1 then the vred must also be 1 : 1. restrictions are: the dredh and aredh must be the same the dredv is equal or smaller than the aredv (e.g dredv i s1:2 and aredv is 1 : 1).
1996 aug 13 17 philips semiconductors preliminary speci?cation picture-in-picture (pip) controller SAB9076H sa 0ah to sa 0ch acquisition fine positioning registers these registers determine the start of the acquisition area. horizontal fine positioning can be adjusted with 16 steps of 2 pixels, vertical fine positioning can be adjusted with 256 steps of 1 line/field. sa 0dh to sa 0eh selection registers the mlsel3 to mlsel0 and slsel3 to slsel0 bits control which pip is live. both main channel and sub-channel can have one live pip. counting is carried out from upper-left to lower-right. the mbsel3 to mbsel0 and sbsel3 to sbsel0 bits control which pip border has a different colour. both main channel and sub-channel can have a different pip channel border selection. counting is done from upper-left to lower-right. sa 0fh border size register this register controls the border size. the minimum horizontal border is 2 pixels. the minimum vertical border is 1 line. the vertical border size is multiplied by the fh mode number before it is displayed on the screen. sa 10h and sa 11h border colour and border select colour of sub - channel registers (see table 5) if sbon is set to logic 1 then the border of the sub-channel is visible. sbbrt and sbcol control the brightness and colour of the sub-channel border colour. if sbson is set to logic 1 then one sub-pip border can have a different colour. this border is selected by the sbsel3 to sbsel0 bits. the sbsbrt and sbscol bits control the brightness and colour off the sub-border selection colour. sa 12h and sa 13h border colour and border selection colour of main channel registers (see table 5) if mbon is set to logic 1 then the border of the main channel is visible. the mbbrt and mbcol bits control the brightness and colour of the main-channel border colour. if mbson is set to logic 1 then one main pip border can have a different colour. this border is selected by the mbsel3 to mbsel0 bits. the mbsbrt and mbscol bits control the brightness and colour off the main-border selection colour. sa 14h background control register (see table 5) if bgon is set to logic 1 then the background is visible. bgbrt and bgcol registers control the brightness and colour of the background colour.
1996 aug 13 18 philips semiconductors preliminary speci?cation picture-in-picture (pip) controller SAB9076H table 5 colour types and brightness levels colour type brightness level colour value 4h 5h 6h 7h black 0h 0% 10% 30% 50% blue 1h 30% 50% 70% 100% red 2h 30% 50% 70% 100% magenta 3h 30% 50% 70% 100% green 4h 30% 50% 70% 100% cyan 5h 30% 50% 70% 100% yellow 6h 30% 50% 70% 100% white 7h 60% 70% 80% 100% table 5 indicates how i 2 c-bus register settings control the colour and brightness. all colour registers are similar, they contain one on/off bit, two brightness bits and three colour type bits. to determine which colour is visible in the event two or more colours being displayed on the same position, the next priority scheme is followed. 1. sub-select colour (sbs) 2. sub-border colour (sb) 3. main-select colour (mbs) 4. main-border colour (mb) 5. background colour (bg). sa 15h and sa 16h decoder registers the mvfilt and svfilt bits can set the type of vertical filtering. the muvpol and suvpol bits invert the uv polarity of the incoming signals. the mvspol and svspol bits determine the active edge of the v sync (see fig.7). mhsync and shsync bits determine the timing of the h sync pulse (burstkey or h sync timing). the mfpol and sfpol bits can invert the field identification (id) of the incoming fields (see fig.7). sa 17h display settings register the fbdel2 to fbdel0 bits can adjust the fast blank delay in 8 steps of 1 2 a clock cycle ( - 8 to +7). 0h is mid-scale. the duvpol bit inverts the uv polarity of the border colours. the dvspol bit determines the active edge of the v sync (see fig.7). the dhsync bit determines the timing of the h sync pulse (burstkey or h sync ). the dfpol bit can invert the field identification of the incoming fields (see fig.7). sa 18h pedestal settings register the pedestu3 to pedestu0 and pedestv3 to pedestv0 bits provide the u and v dac outputs an offset of - 8 to +7 lsb when the fbl is switched off. this can be used to adjust the white point of the system.
1996 aug 13 19 philips semiconductors preliminary speci?cation picture-in-picture (pip) controller SAB9076H additional i 2 c-bus settings table 6 overview of additional i 2 c-bus sub-addresses note 1. the data bits which are not used should be set to zero. sa data byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 20h prio note 1 note 1 note 1 mvrpn1 mvrpn0 svrpn1 svrpn0 21h mhrpo31 mhrpo30 mhrpo21 mhrpo20 mhrpo11 mhrpo10 mhrpo01 mhrpo00 22h mhrpn31 mhrpn30 mhrpn21 mhrpn20 mhrpn11 mhrpn10 mhrpn01 mhrpn00 23h mhpic7 mhpic6 mhpic5 mhpic4 mhpic3 mhpic2 mhpic1 mhpic0 24h mvpic7 mvpic6 mvpic5 mvpic4 mvpic3 mvpic2 mvpic1 mvpic0 25h mhdis07 mhdis06 mhdis05 mhdis04 mhdis03 mhdis02 mhdis01 mhdis00 26h mhdis17 mhdis16 mhdis15 mhdis14 mhdis13 mhdis12 mhdis11 mhdis10 27h mhdis27 mhdis26 mhdis25 mhdis24 mhdis23 mhdis22 mhdis21 mhdis20 28h mhdis37 mhdis36 mhdis35 mhdis34 mhdis33 mhdis32 mhdis31 mhdis30 29h mvdis7 mvdis6 mvdis5 mvdis4 mvdis3 mvdis2 mvdis1 mvdis0 2ah shrpo31 shrpo30 shrpo21 shrpo20 shrpo11 shrpo10 shrpo01 shrpo00 2bh shrpn31 shrpn30 shrpn21 shrpn20 shrpn11 shrpn10 shrpn01 shrpn00 2ch shpic7 shpic6 shpic5 shpic4 shpic3 shpic2 shpic1 shpic0 2dh svpic7 svpic6 svpic5 svpic4 svpic3 svpic2 svpic1 svpic0 2eh shdis07 shdis06 shdis05 shdis04 shdis03 shdis02 shdis01 shdis00 2fh shdis17 shdis16 shdis15 shdis14 shdis13 shdis12 shdis11 shdis10 30h shdis27 shdis26 shdis25 shdis24 shdis23 shdis22 shdis21 shdis20 31h shdis37 shdis36 shdis35 shdis34 shdis33 shdis32 shdis31 shdis30 32h svdis7 svdis6 svdis5 svdis4 svdis3 svdis2 svdis1 svdis0 in manual mode more pip modes become available with the help of register 20h to 32h. an overview of these i 2 c-bus registers is given in table 6. the meaning and relation of the i 2 c-bus registers is shown in fig.8. the background has a fixed size and can be fine positioned with the bghfp and bghfp bits. the shown pips are only for one channel (main or sub), the other channel has the same control and can be displayed at the same time. the sdhfp and mdhfp bits determine the most left shown pixel for this channel in 256 steps of 4 pixels. the sdvfp and mdvfp bits determine the most upper shown line for this channel in 256 steps of 1 line. the shpic and mhpic bits determine the horizontal picture size in 256 steps of 4 pixels, the minimum value is 4 pixels. the svpic and mvpic bits determine the vertical picture size in 256 steps of 1 line, the minimum value is 1 line. the pip mode is built-up of a maximum of four horizontal rows. the minimum is one row, more rows can be displayed by setting the vertical repetition rate number vrpn bits. the distance between the rows can be set by svdis and mvdis bits. every row is built-up of a maximum of four pips. the minimum is one pip and the distance between the starting points of those pips on a row is determined by shdis and mhdis bits. sa 20h control register the prio bit sets the priority between main and sub channel. if prio is set to logic 0, priority is given to the sub channel which means that the sub channel pips, if present, are placed on top of the main pips. if prio is set to logic 1, the main pips are set on top of the sub pips. the mvrpn and svrpn bits determine the number of repeated pip rows. there is always one row visible of each channel. if no pips should be visible the pip channel must be switched off (sa 00, bit 7 or bit 6).
1996 aug 13 20 philips semiconductors preliminary speci?cation picture-in-picture (pip) controller SAB9076H sa 21h and sa 2ah h orizontal r epetition o ffset registers for row 0 to 3 the horizontal repetition offsets (mhrpo and shrpo bits) are strongly related to the horizontal distance (mhdis and shdis bits). these registers set for each row a certain grid of possible starting points for the pips in that row. every grid point has a number 0 (the most left pip), 1, 2 or 3. the mhrpo and shrpo bits determine the first pip number which will be displayed. this mechanism can be set for each row. sa 22h and sa 2bh h orizontal r epetition n umber registers for row 0 to 3 the horizontal repetition numbers (mhrpn and shrpn bits) determine how many times the pips are repeated in a row, once the first pip is displayed. the repeated pips stay in the grid determined by the mhdis and shdis bits for that row. this mechanism can be set for each row independent. sa 23h and sa 24h; sa 2ch and sa 2dh p icture size registers the mhpic and shpic bits determine the horizontal pip size in 256 steps of 4 pixels. the mvpic and svpic bits determine the vertical pip size in 256 steps of 1 line. sa 25h and sa 29h; sa 2eh and sa 32h p icture d istance registers for each row the distance between starting points of pips can be set with the bits mhdis and shdis in 256 steps of 4 pixels. the distance between two rows can be set with the mvdis and svdis bits in 256 steps of 1 line. acquisition channel adcs both channels convert the analog input signals to digital signals by means of two adcs for each channel. the input levels of the adcs of each channel are equal and can be set by the av reft and av refb pins. the reference levels are made internally by a resistor network which divides the analog supply voltage to a default set of preferred levels. external capacitors are needed to filter ac components on the reference levels. the resolution of the adcs is 8 bit. differential non-linearity (dnl) is 7-bit; integral non-linearity (inl) is 6-bit, and the sampling is carried out at the system frequency of 27 mhz for the y input. the u/v inputs are multiplexed and sampled at 13.5 mhz. the analog input signals are amplified to make maximum use of the dynamic range of the adcs. a bias voltage v bias is used for decoupling ac components on internal references. the inputs should be ac-coupled and an internal clamping circuit will clamp the input to av refb for the luminance channels and to for the chrominance channels. the clamping starts at the active edge of the burst key. output dacs the digitally processed signals are converted to analog signals by three 8-bit dacs. the output voltages of these dacs are default set by the dav reft pin for the top level and dav refb pin for the bottom level. default values are 1.5 v. external memory for the external memory two vdrams of type mitsubishi m5m442256 are used. they have a storage capacity of 262 144 words of 4-bit each and will be used in parallel. it is also possible to use a 2 mbit vdram with a storage capacity of 262 144 words of 8 bit each. an overview of the timing diagrams is given in fig.9. av reft av refb C 2 ----------------------------------------- lsb 2 ----------- - +
1996 aug 13 21 philips semiconductors preliminary speci?cation picture-in-picture (pip) controller SAB9076H fig.7 vertical synchronization timing and field identification. handbook, full pagewidth mbe100 432 389 43 1st field 2nd field field id (internal) (number of pixels) h (external) sync v (external) sync v (external) sync handbook, full pagewidth mgd583 bghfp bgvfp dvfp vpic vdis hdis dhfp hpic 1 + vrpn rows 1 + hrpn columns fig.8 relation of display i 2 c-bus register.
1996 aug 13 22 philips semiconductors preliminary speci?cation picture-in-picture (pip) controller SAB9076H fig.9 vdram timing handbook, full pagewidth mgc970 ad0 to ad8 row column column column column column write cycle (main or sub) we dao0 to dao7 cas ras clock ad0 to ad8 row column read cycle we dt cas ras clock cas ras clock refresh cycle sc dai0 to dai7 shift clock cycles (2) (2) (1) (1) clock = 13.5 mhz. (2) clock = 27 mhz.
1996 aug 13 23 philips semiconductors preliminary speci?cation picture-in-picture (pip) controller SAB9076H limiting values in accordance with the absolute maximum rating system (iec 134). note 1. human body model: see uzw-b0/fq-b302 ; the numbers of the quality specification can be found in the quality reference handbook . the handbook can be ordered using the code 9397 750 00192. 2. machine model: see uzw-b0/fq-a302 ; the numbers of the quality specification can be found in the quality reference handbook . the handbook can be ordered using the code 9397 750 00192. thermal characteristics quality specification in accordance with snw-fq-611 part e . the numbers of the quality specification can be found in the quality reference handbook . the handbook can be ordered using the code 9397 750 00192. symbol parameter min. max. unit v dd supply voltage - 0.5 +6.5 v p max maximum power dissipation - 1.5 w t stg storage temperature - 25 +150 c t amb operating ambient temperature - 25 +70 c v esd electrostatic discharge handling human body model 3000 (1) v machine model 300 (2) v symbol parameter conditions value unit r th j-a thermal resistance from junction to ambient in free air 34 k/w
1996 aug 13 24 philips semiconductors preliminary speci?cation picture-in-picture (pip) controller SAB9076H characteristics v dd = 5.0 v; t amb =25 c; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supply v dd all positive supply voltages 4.5 5.0 5.5 v v ss all ground voltages - 0 - v d v dd(max) maximum difference between supply voltages - 0 100 mv d v ss(max) maximum difference between ground voltages - 0 100 mv i dddq quiescent current of digital supply voltages note 1 - 050 m a i mpvdda main pll supply current - 6 - ma i spvdda sub pll supply current - 6 - ma i dpvdda display pll supply current - 6 - ma i mavdda main adcs supply current - 40 - ma i savdda sub adcs supply current - 40 - ma i davdda display dacs supply current - 20 - ma i dda(tot) total analog supply current - 115 - ma i ddd(tot) total digital supply current - 100 - ma analog-to-digital converter and clamping v reft top reference voltage note 2 1.9 2.1 2.3 v v refb bottom reference voltage note 2 0.3 0.4 0.5 v v i(y,u,v)(p-p) input signal amplitude (peak-to peak value) note 2 1.2 1.5 1.6 v i i input current clamping off - 0.1 -m a clamping on - 100 -m a c i input capacitance - 5 - pf f s sample frequency rate note 3 - 1728hs - mhz res resolution 6 8 - bit dnl differential non-linearity - 2.0 - +2.0 lsb inl integral non-linearity - 4.0 - +4.0 lsb a cs channel separation - 48 - db psrr power supply rejection ratio - 48 - db v clampy clamping voltage level y note 4 - v refb - v v clampuv clamping voltage level u/v - note 5 - v
1996 aug 13 25 philips semiconductors preliminary speci?cation picture-in-picture (pip) controller SAB9076H notes 1. digital clocks are silent, por is v dd . 2. the v reft and v refb are made by a resistor division of the v dd . they can be calculated with the formulas: and the analogue supply voltages are 5 v. 3. the internal system frequency is 1728 times the h sync input frequency for both the acquisition and display plls. 4. the y-channel is clamped to the v refb of the adcs. 5. the uv-channel is clamped to 1 / 2 (v reft +v refb +v lsb ). 6. the gain of the SAB9076H is 1 under the condition that the r l is 220 w . digital-to-analog converter and output stage v reft top reference voltage 2.2 2.3 2.4 v v refb bottom reference voltage 0.3 0.4 0.5 v v o(y,u,v) output signal amplitude note 6 - 1.5 1.6 v r l load resistance note 6 75 220 10 10 3 w c l load capacitance 0 - 50 pf f s sample frequency rate note 3 - 1728hs - mhz res resolution 6 8 8 bit dnl differential non-linearity - 1.0 - +1.0 lsb inl integral non-linearity - 1.0 - +1.0 lsb a cs channel separation - 48 - db psrr power supply rejection ratio - 48 - db pll and clock generation acquisition f i(pll) input frequency note 3 14 15.75 18 khz pll and clock generation display f i(pll) input frequency note 3 14 15.75 18 khz symbol parameter conditions min. typ. max. unit v reft av dd 2.0 5.0 ------- - ? ?? v = v refb av dd 0.4 5.0 ------- - ? ?? v =
1996 aug 13 26 philips semiconductors preliminary speci?cation picture-in-picture (pip) controller SAB9076H dc characteristics for the digital part v ddd = 4.5 to 5.5 v (all v ddd pins); t amb = - 20 to +75 c; unless otherwise speci?ed. note 1. v i is attached to the v ddd or v ssd . ac characteristics for the digital part v ddd = 4.5 to 5.5 v (all v ddd pins); t amb = - 20 to +75 c; unless otherwise speci?ed. note 1. the internal system frequency is1728 times the h sync input frequency for both the acquisition and display plls. symbol parameter conditions min. typ. max. unit v ih high level input voltage hpf01 70 -- %v dd hpp01 70 -- %v dd hup07 80 -- %v dd ioi41 70 -- %v dd v il low level input voltage hpf01 -- 30 %v dd hpp01 -- 30 %v dd hup07 -- 20 %v dd ioi41 -- 30 %v dd v hys hysteresis voltage hup07 - 33 - %v dd v oh high level output voltage opf20; i ol = - 2 ma; v ddd = 4.5 v 4.1 -- v v ol low level output voltage ioi41; i ol = +4 ma; v ddd = 4.5 v -- 0.4 v opf20; i ol = +2 ma; v ddd = 4.5 v -- 0.4 v ? i li ? input leakage current hpf01; v ddd = 5.5 v; note 1 - 0.1 1 m a hpp01; v ddd = 5.5 v; note 1 - 0.1 1 m a ? i oz ? 3-state output leakage current ioi41; v ddd = 5.5 v; note 1 - 0.2 5 m a r pu internal pull-up resistor hup07 17 - 134 k w symbol parameter conditions min. typ. max. unit f sys system frequency acquisition; note 1 - 27 30 mhz display; note 1 - 27 30 mhz t r rise time - 625ns t f fall time - 625ns
1996 aug 13 27 philips semiconductors preliminary speci?cation picture-in-picture (pip) controller SAB9076H test and application information the application diagram for 1 fh mode in a standard configuration is shown in fig.10. two input signals mcvbs and scvbs of different sources are processed by the SAB9076H and inserted by the yuv/rgb switch. the synchronization of the display pll is derived from the deflection circuit. the main signals are also fed to the deflection circuit and the yuv/rgb switch where the SAB9076H signals can be inserted. the signals for deflection can also be taken from the main channel or sub-channel decoder. fig.10 application diagram for 1 fh mode. h andbook, full pagewidth mgc971 yuv to rgb y u v r g b flb vs hs (1 fh) SAB9076H y u v hs vs decoder main mcvbs y u v hs vs decoder sub scvbs vdram 2 mbit hs vs y main signals u v yuv/rgb switch and deflection circuit r g b hs vs
1996 aug 13 28 philips semiconductors preliminary speci?cation picture-in-picture (pip) controller SAB9076H fig.11 application diagram. all capacitors are 100 nf. on the application board a ground plane should be used. handbook, full pagewidth 1 mpv bias mav bias mav refb mav reft mav dda mav ssa mv ddd mcv ddd mcv ssd mv ssd mv mu tdclk taclk tc tm0 tm1 n.c. my mpv dda mav ddd mav ssd mpv ssa mph sync mv sync spv bias sav bias sav refb sav reft sav dda sav ssa sv ddd scv ddd scv ssd sv ssd sv su por sda scl a0 sy spv dda sav ddd sav ssd spv ssa sph sync sv sync dpv ssa dav dda dav ssa dav ssd dav ddd dpv dda dpv bias dav bias dav reft dav refb dph sync dv sync dfb du dv ddd dv ssd dcv ddd dcv ssd v ddd v ssd dao0 to dao7 ras cas we dt sc ad0 to ad8 dai0 to dai7 dv dy 5 4 3 11 12 14 13 15 16 18 63 19 20 21 22 2 hout cvbs/y cvbs/y main-channel input cvbs/y sub-channel input vout tda8315t SAB9076H - v - u y hout cvbs/y vout tda8315t - v - u y 99 100 97 98 91 + 5 v + 5 v + 5 v 80 82 81 77 78 79 64 76 73 72 75 74 71 70 69 67 68 66 65 62 + 5 v + 5 v + 5 v + 5 v + 5 v + 5 v + 5 v + 5 v + 5 v + 5 v + 5 v 92 84 83 96 89 95 94 93 90 87 88 85 86 8 9 6 7 10 17 59 46 mgc972 45 + 5 v 42 41 + 5 v 43 44 49 48 47 31 2 mbit memory 40 32, 34, 36, 38, 39, 37, 35, 33 23, 25, 27, 29, 30, 28, 26, 24 51, 53, 55, 57, 58, 56, 54, 52, 50 61 60 9 8 8
1996 aug 13 29 philips semiconductors preliminary speci?cation picture-in-picture (pip) controller SAB9076H package outline unit a 1 a 2 a 3 b p ce (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm 0.25 0.05 2.90 2.65 0.25 0.40 0.25 0.25 0.14 14.1 13.9 0.65 18.2 17.6 1.4 1.2 1.0 0.6 7 0 o o 0.15 0.1 0.2 1.95 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 1.0 0.6 sot317-2 92-11-17 95-02-04 d (1) (1) (1) 20.1 19.9 h d 24.2 23.6 e z 0.8 0.4 d e q e a 1 a l p q detail x l (a ) 3 b 30 c b p e h a 2 d z d a z e e v m a 1 100 81 80 51 50 31 pin 1 index x y b p d h v m b w m w m 0 5 10 mm scale qfp100: plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm sot317-2 a max. 3.20
1996 aug 13 30 philips semiconductors preliminary speci?cation picture-in-picture (pip) controller SAB9076H soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). re?ow soldering reflow soldering techniques are suitable for all qfp packages. the choice of heating method may be influenced by larger plastic qfp packages (44 leads, or more). if infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. for more information, refer to the drypack chapter in our quality reference handbook (order code 9397 750 00192). reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. wave soldering wave soldering is not recommended for qfp packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. if wave soldering cannot be avoided, the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. even with these conditions, do not consider wave soldering the following packages: qfp52 (sot379-1), qfp100 (sot317-1), qfp100 (sot317-2), qfp100 (sot382-1) or qfp160 (sot322-1). during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1996 aug 13 31 philips semiconductors preliminary speci?cation picture-in-picture (pip) controller SAB9076H definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
internet: http://www.semiconductors.philips.com philips semiconductors C a worldwide company ? philips electronics n.v. 1996 sca51 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 926 5361, fax. +7 095 564 8323 singapore: lorong 1, toa payoh, singapore 1231, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. +27 11 470 5911, fax. +27 11 470 5494 south america: rua do rocio 220, 5th floor, suite 51, 04552-903 s?o paulo, s?o paulo - sp, brazil, tel. +55 11 821 2333, fax. +55 11 829 1849 spain: balmes 22, 08007 barcelona, tel. +34 3 301 6312, fax. +34 3 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 632 2000, fax. +46 8 632 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2686, fax. +41 1 481 7730 taiwan: philips taiwan ltd., 23-30f, 66, chung hsiao west road, sec. 1, p.o. box 22978, taipei 100, tel. +886 2 382 4443, fax. +886 2 382 4444 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. +90 212 279 2770, fax. +90 212 282 6707 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 181 730 5000, fax. +44 181 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 825 344, fax.+381 11 635 777 for all other countries apply to: philips semiconductors, marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 34 waterloo road, north ryde, nsw 2113, tel. +61 2 9805 4455, fax. +61 2 9805 4466 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 1 60 101, fax. +43 1 60 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 200 733, fax. +375 172 200 773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 689 211, fax. +359 2 689 102 canada: philips semiconductors/components, tel. +1 800 234 7381 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. +45 32 88 2636, fax. +45 31 57 1949 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 615 800, fax. +358 615 80920 france: 4 rue du port-aux-vins, bp317, 92156 suresnes cedex, tel. +33 1 40 99 6161, fax. +33 1 40 99 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 23 53 60, fax. +49 40 23 536 300 greece: no. 15, 25th march street, gr 17778 tavros, tel. +30 1 4894 339/911, fax. +30 1 4814 240 hungary: see austria india: philips india ltd, shivsagar estate, a block, dr. annie besant rd. worli, mumbai 400 018, tel. +91 22 4938 541, fax. +91 22 4938 722 indonesia: see singapore ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, piazza iv novembre 3, 20124 milano, tel. +39 2 6752 2531, fax. +39 2 6752 2557 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108, tel. +81 3 3740 5130, fax. +81 3 3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381 middle east: see italy printed in the netherlands 537021/50/01/pp32 date of release: 1996 aug 13 document order number: 9397 750 01016

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